Senior Test Development Engineers with J750 experience

Salary: Very Attractive Rate
Senior Test Development Engineers 
Chipright seeks a highly motivated and experienced test engineer to work in validating our Irish customer’s latest design using J750. The candidate should have hands on experience in debugging silicon tests and must be proficient with ATE Engineering, Product Characterization & qualification testing.
  • Plan and arranges the labor, schedules, and equipment required for testing and evaluating standard and special devices.
  • Provide test area with parameters for sampling testing and specifies tests to be performed.
  • Compile data and defines changes required in testing equipment, testing procedures, manufacturing processes, or new testing requirements.
  • Test all customer samples and for special tests that cannot be performed in the test area.
  • Respond to customer/client requests or events as they occur.
  • Develops solutions to problems utilizing formal education and judgement.
  • Work closely with various Design teams' programmable logic, memory, digital IP, analog and high-speed SERDES from the initial IP/product planning phase through design implementation and verification.
  • Define test methodologies, developing test benches & run simulations, deploy test patterns and validating them on silicon.
  • Supports product teams with yield improvement and interface characterization.
  • The engineer may be able to work part remote (for eg. 3 days onsite/ 2 days offsite)
  • BSEE with 6+ years test program development experience
  • Fully understand digital testing and DFx
  • Knowledge of ATE tester with programming skills
  • Hi-Speed SERDES test experience- Script TCL/PERL/Python and programming languages Visual Basic and C/C++
  • Hands-on problem solving skills including hardware and software
  • Preferred Qualifications:
  • MSEE with 6+ years test program development experience
  • Test experience with digital/analog/mix-signal products
  • Teradyne J750 and Advantest test development skills
  • Full understanding of DFx implementation and debugging of SCAN/BIST
  • Pre-silicon simulation experience and tools of pattern conversion
  • Team technical lead


  • Test Engineering
  • Post Silicon
  • Tcl
  • perl
  • python
  • C
  • C++
  • DFT
  • DFM
  • Validation
  • Process Characterization
  • Device Characterization
  • Test strategies
  • Test Plans
  • ATPG
  • BIST
  • SCAN
  • JLCC
  • JTAG
  • ATE
  • Debugging
  • Schematic Capture
  • PCB layout
  • Test Vectors+-