Senior Analog IC Layout Engineer with finFET experience

Salary: Very Attractive Rate
Location: N/A
Contract 
Senior Analog Layout Engineers - 4-5 Engineers 

    
 	
  • Minimum 7 year's experience in Analog IC Layout
    • 
 	
  • Experience working on High Speed Layout
    • 
 	
  • Experience working on speeds up to or past 25 Gb/ sec
    • 
 	
  • Experience working on finFET technology/ TSMC down to 16nm
    • 
 	
  • Experience using Cadence tools
    • 


Chipright – Your Partner in finding that next job – Call us on +353 91 444168 or Email annette.burke@chipright.com

Skills

  • Analog
  • RF
  • AMS
  • Analog
  • CMOS
  • SiGe
  • NMOS
  • PMOS
  • BiCMOS
  • BiPolar
  • LNAs
  • Mixers
  • LDOs
  • drivers
  • VCOs
  • PLLs
  • RF Transceivers
  • millimetre-wave Design
  • High Speed
  • finFET
  • FF
  • mmWave Design
  • K band
  • Ku band
  • Ka band
  • Labview
  • RF Test
  • Advantest
  • Layer 1
  • LTE
  • 4G
  • 3G
  • Design Packages
  • WCDMA
  • BiCMOS
  • CMOS
  • BiPOLAR