ASIC Verification

Salary: Very Attractive Rate
Location: Sweden
ASIC Verification Engineer-systemverilog

Chipright seeks highly motivated and experienced verification engineers to work in validating block and system level IP. We require engineers to work with leading-edge technologies in delivering robust and reliable IP. This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers. 

YOUR ROLES:
7+ years experience in verification of complex SoC level ASIC
Proficient with SystemVerilog & SV classes UVM
Experience with constrained-random verification methodologies
Development of verification environment based on Object Orientated techniques
Development of functional coverage points and reporting mechanisms
Scripting in Tcl / Perl
Ability to develop a verification test plan and test bench
Strong debug & problem-solving skills
Experience with EDA tools for developing / working with register models & functional coverage development

DESIRABLE:
Formal Verification , Assertion based techniques (SVA, PSL, OVAL)
Power Aware verification, UPF knowledge & Gate Level simulation
Experience with one or more HVLs (SystemVerilog, VHDL, Vera, e / Specman, SystemC)
Experience with Radio related ASIC
 

Skills

  • SystemVerilog
  • OVM
  • UVM
  • VMM
  • Verilog
  • VHDL
  • SVA
  • Assertions
  • OVAL
  • PSL
  • Verification engineer
  • Constrained Random
  • Functional Coverage
  • UPF
  • Power aware
  • Tcl
  • perl
  • python
  • C
  • C++
  • Vera
  • Specman
  • e
  • Consultant
  • Contractor
  • Full time
  • permanent
  • Freelancer
  • Questa
  • NCSIM
  • VCS
  • Digital
  • ASIC
  • FPGA
  • SoC
  • Architecture