Analog & Mixed Signal Designer with SAR ADC Design experience

 	
Vast experience working on updates to an existing SAR ADC interface
 	
The low-level interface to this ADC must be redesigned to work with a new ADC currently being designed.
 	
There is also a input mux to the ADC which has expanded. The interface handles control of this mux, and has configurable priority to different sources.
 	
The ADC is going to be instantiated twice in the design, and additional flexibility is needed to support the second use case.
 	
There is an existing SystemVerilog/UVM testbench for the ADC which can be updated and used to verify the changes.
 	
The ADC interface must be integrated into the design in both locations where it is required.
 	
Chip-level tests to verify its correct integration should be updated, and new ones added for the second instantiation.