Analog IC Layout Engineer

Salary: Attractive Rate
Location: N/A
Contract
Senior Analog IC Layout Engineer
  • Experienced analog IC layout,
  • Coarse geometry, 0.35um CMOS
  • Experience in Cadence tools , ASSURA DRC LVS , PVS DRC LVS, and QRC
  • Experience in Mentor Calibre Tools DRC LVS and Parasitic Extraction

Skills

  • Analog
  • RF
  • AMS
  • Analog
  • CMOS
  • SiGe
  • NMOS
  • PMOS
  • BiCMOS
  • BiPolar
  • LNAs
  • Mixers
  • LDOs
  • drivers
  • VCOs
  • PLLs
  • RF Transceivers
  • millimetre-wave Design
  • High Speed
  • finFET
  • FF
  • mmWave Design
  • K band
  • Ku band
  • Ka band
  • Labview
  • RF Test
  • Advantest
  • Layer 1
  • LTE
  • 4G
  • 3G
  • Design Packages
  • WCDMA
  • BiCMOS
  • CMOS
  • BiPOLAR